In general, when using multiple banks of memory modules in a memory system of a data processor, in order to access such memory banks to perform read and write operations, information which is being transferred to or from the memory system is often transferred in the form of multiple data word blocks. For example, it is common to transfer information in blocks of four 32-bit data words, either for writing into or reading from the memory modules. A conventional approach to such a data transfer operation is to utilize four banks of memory modules and to access one of the four words from each memory module bank in sequence. During each read access, for example, error detection and correction logic is utilized in association with each module bank in order to check the data words involved for single or multiple bit errors.
The overall performance for such a conventional approach is acceptable when using high speed memory systems, but at a cost which is commensurate with the number and the quality of the components which are used therein. It is desirable in some applications to achieve equivalent performance at a lower cost by using fewer components and lower speed memory modules than those required in current systems.